There’s perhaps no field more demanding than modern semiconductor design. In both research and commercial settings, customers expect new electronic devices to be faster, cheaper, smaller, and more energy-efficient with each generation. Semiconductor producers rely on electronic design automation (EDA) tools to realize these improvements.

Few understand these challenges better than CEA Tech, the Grenoble-based technology research unit for the French Alternative Energies and Atomic Energy Commission (CEA). CEA Tech is a global leader in multiple disciplines, including miniaturization, energy efficiency, micro-electromechanical systems (MEMS), photonics, and more. It is a catalyst and innovation accelerator that brings advanced technologies to industry in France to improve product performance and competitiveness. CEA Tech was recently the subject of an Altair customer story; in it, the organization demonstrated simulation throughput gains ranging from 3.9 to 4.5x using Altair’s advanced workload management solutions.

Semiconductor Design Challenges

Chip designers face unprecedented challenges bringing new designs to market. Gate counts continue to grow, as do customer expectations related to performance, cost, quality, and battery life. Verification is the process of ensuring that designs perform as expected, and it’s one of the most demanding workloads in EDA. Every time a design is changed, it must be simulated and revalidated to ensure its functionality doesn’t regress. With fabrication costs running into the millions of dollars, designs need to be flawless before tapeout. Fixing bugs after a design is committed to silicon simply isn’t an option.

Verification complexity varies exponentially with the number of gates. It’s not uncommon for large system-on-a-chip (SoC) designs to feature gate counts in the tens of billions. Compounding these verification challenges are stringent requirements around quality and reliability. Among the sectors that CEA serves are manufacturers of medical and Internet of Things (IoT) devices and firms in the energy and defense sectors, where devices are often life-critical. 

Never Enough Compute

Producing high-quality products requires extensive simulation. While design innovations matter, manufacturers also compete based on their verification environments’ effectiveness. By some estimates, regression testing and verification account for roughly 80% of all EDA workloads. Faced with intense competition, aggressive time-to-market goals, and shorter design cycles, firms must maximize design coverage and turn regression tests around quickly.

While the appetite for compute capacity is practically unlimited, organizations face real-world constraints. These include finite IT budgets, data center space, and limited power and cooling capacity. As Moore’s law has stalled, verification engineers increasingly rely on increased parallelism and new verification techniques to keep pace with design complexity. The high cost of EDA software tools is also a limiting factor. Individual software features are frequently more expensive than the servers they run on. Designers need to maximize license usage, share them equitably, and minimize checkout time so that features are freed quickly and made available to queued jobs. 

The Importance of Throughput and Turnaround Time

In a field where even single-digit throughput gains are a big deal, improvements of about 4x – such as those achieved by CEA – are almost unheard of. These gains prove the wisdom of the old adage “work smarter, not harder.” Firms can maximize license usage by leveraging EDA-optimized scheduling tools such as Altair Accelerator to place verification jobs optimally on the most appropriate hosts. They can also bolster verification throughput and reduce wait times, directly improving engineering productivity.  

High-Throughput Verification Yields Multiple Benefits

What if every semiconductor design firm could realize a nearly 4x gain in simulation throughput? The benefits of higher verification throughput extend well beyond the design environment. They impact the business overall, affecting various metrics related to financial performance competitiveness. Not only can faster simulations shorten product cycles and improve time-to-market, they help organizations “fail faster.” What this means is engineers are free to explore new design approaches, see what works, and implement it. Doing this quicker and more efficiently fosters an innovative, fast-moving culture and brings other benefits, including:

• Higher-quality designs that improve competitiveness by boosting revenue and market share
• Faster turnaround times that enable engineers to more thoroughly explore the design space and deliver more features in less time
• More thorough testing results that improve customer satisfaction, lead to fewer fields defects, and reduce warranty and support costs
• Improved agility and the ability to react more quickly to external competitors, shifts in customer demand, and changing market conditions

In addition to productivity gains, there are financial benefits as well. By sharing license features and infrastructure more efficiently, organizations can avoid new spending and maximize their return on existing assets. The combination of improved productivity and reduced spending can be a boon to any company’s bottom line. To the extent that organizations can replicate even some of the efficiency gains realized by CEA Tech, they can dramatically improve their productivity and competitiveness.

The Future of EDA Simulations

Despite the challenges detailed above, semiconductor design innovation shows no signs of slowing. To simulate designs faster, design teams are now looking beyond software-based simulators. They are investing in hardware-assisted verification technologies such as FPGA-based emulators, prototyping platforms, and GPU-accelerated tools. Large-scale emulators can dramatically improve throughput, but they also bring new challenges. For example, emulators are significantly more expensive than software-based approaches; it can take days to compile and load a new design into an emulator. Organizations increasingly require scheduling solutions that can optimize all types of resources, including hardware, software, emulators, and prototyping platforms. 

To learn more about how the CEA improved its simulation environment, download the customer story. And to learn more about Altair solutions for EDA software and hardware-assisted verification environments, visit the web pages for Altair Accelerator and Altair Hero.